In general, a strong need exists to reduce power dissipation in computer systems. This requirement is particularly significant in respect to handheld devices and notebook computers for applications or situations in which the device is not connected to an external supply voltage. Several prior art methods realize power savings by switching off or idling discrete sub-systems of a microprocessor or other integrated circuit device when such sub-systems are inactive for a given period of time, e.g. pressing a key or moving a mouse pointer, etc. Another technique to reduce power dissipation in computer systems is based on tailoring the operation of the device to reduce unnecessary operations that contribute to power dissipation.
In modern storage array designs several storage cells are connected to one write-head and one read-head in the form of a sense amplifier via pairs of bitlines (BL), whereby each pair of bitlines consists of one “true” and one “complement” bitline. For fast access time and low power consumption the bitlines are precharged, according to prior art technology, each cycle to read data from and write data to the cells. A separate signal input controls whether data is written or read. In a differential write and read access memory scheme with true and complement bitlines, one bitline must be drawn to high and the other must be drawn to zero independently of the bit value to be written. The precharge may be accomplished with respect to a single memory cell, or an entire segment comprising a sub-array of memory cells.
With specific reference to the aspect of power saving during operation it should be noted that prior art differential writing entails a complete discharge of one bitline of the regarded bitline pair. This is depicted in FIG. 1, where a bitline TRUE denoted as BLT, is drawn to logic “0” level at time t=t1, t3 or bitline COMPLEMENT denoted as BLC, is drawn to logic “0” level at time t=t5, t7, etc. By way of contrast, reading discharges the bitline only partly, see bitline COMPLEMENT BLC at t=t8. Directly after the data is written or read, the bitlines are usually precharged for the following cycle in a so-called restore process, as in FIG. 1 at time t=t2, t4, t6, t9, etc.
The prior art precharging techniques count for a significant amount of power dissipated in the memory array since an array comprises a large number of bitlines and each of them is relatively long. The power consumption for a read cycle is lower than for a write cycle because the bitlines are not totally discharged in the read cycle case. It should be noted, however, that complementary system hardware, such as power supply or test equipment must be designed for peak array power during the case of a write operation. Since the total chip power is typically composed of clock power (40%), array power (40%) and power for logic (20%), it is evident that a reduction in power dissipated by the memory array may lead to a significant reduction in total power.
U.S. Pat. No. 5,848,015 assigned to Sony Corporation discloses a specific technique for reducing the power consumed during sequential read access operations of the memory cells within a memory block. According to this prior art approach, power saving is limited because it is first restricted to read access operations and does not include write access operations, and second this technique basically delays the time at which precharging takes place, namely when the memory access to the last memory cell within a given row is complete. Accordingly, this method can only be applied in particular applications in which a sequential read of the memory cells within one and the same row of a given memory block occurs over several cycles. In the general case, however, in which the access is non-sequential, cycle-selective and directed to a complete segment of an array—as it is the case with the most state of the art memory cells—this prior art method can not be efficiently applied. Further, this prior art disclosure leaves out the possibility to save power during write operations.